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| an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tps7a05 sbvs254b ? february 2018 ? revised august 2018 tps7a05 1- a ultralow i q , 200-ma, low-dropout regulator in a small-size package 1 1 features 1 ? ultralow i q : 1 a (typ), 3 a (max) ? i gnd : 6 a (typ) at 200 ma ? excellent transient response ? packages: ? 1.0-mm 1.0-mm x2son (4) ? 0.65-mm 0.65-mm dsbga (4) ? sot-23 (5) ? input voltage range: 1.4 v to 5.5 v ? output accuracy: 1% typical, 3% maximum ? available in fixed-output voltage: ? 0.8 v to 3.3 v ? very low dropout: ? 235 mv (max) at 200 ma (3.3 v out ) ? active output discharge ? foldback current limit ? stable with a 0.47- f or larger capacitor 2 applications ? wearable electronics ? ultrabooks, tablets, ereaders ? always-on power supplies ? set-top boxes ? gaming controllers, remote controls, toys, drones ? wireless handsets and smart phones ? portable and battery-powered equipment 3 description the tps7a05 is an ultra-small, low quiescent current low-dropout regulator (ldo) that can source 200 ma with excellent transient performance. this device has an output range of 0.8 v to 3.3 v with a typical 1% accuracy. the tps7a05, with ultralow i q (1 a), consumes very-low quiescent current for extending battery life in battery-powered applications. the device can be operated from rechargeable li-ion batteries, li- primary battery chemistries such as li-socl2, li- mno2, as well as two- or three-cell alkaline batteries. the tps7a05 is available with an active pulldown circuit to quickly discharge the output when disabled. the tps7a05 is fully specified for t j = ? 40 c to +125 c operation, and is available in standard x2son (dqn), sot-23 (dbv), and dsbga (yka) packages. device information (1) part number package body size (nom) tps7a05 x2son (4) 1.00 mm 1.00 mm dsbga (4) 0.65 mm 0.65 mm sot-23 (5) 2.90 mm 1.60 mm (1) for all available packages, see the package option addendum at the end of the data sheet. typical application circuit ground current vs output current tps7a05 in en out gnd c out c in on off output current (ma) ground current ( p a) 0 20 40 60 80 100 120 140 160 180 200 0 1 2 3 4 5 6 7 d043 tools & software technical documents ordernow productfolder support &community
2 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 switching characteristics .......................................... 6 6.7 typical characteristics .............................................. 7 7 detailed description ............................................ 15 7.1 overview ................................................................. 15 7.2 functional block diagram ....................................... 15 7.3 feature description ................................................. 16 7.4 device functional modes ........................................ 18 8 application and implementation ........................ 19 8.1 application information ............................................ 19 8.2 typical application .................................................. 24 9 power supply recommendations ...................... 24 10 layout ................................................................... 25 10.1 layout guidelines ................................................. 25 10.2 layout example .................................................... 25 11 device and documentation support ................. 26 11.1 device support ...................................................... 26 11.2 documentation support ........................................ 26 11.3 receiving notification of documentation updates 26 11.4 community resources .......................................... 26 11.5 trademarks ........................................................... 26 11.6 electrostatic discharge caution ............................ 26 11.7 glossary ................................................................ 26 12 mechanical, packaging, and orderable information ........................................................... 27 4 revision history changes from revision a (may 2018) to revision b page ? changed 1-mm 1-mm to small-size in document title ....................................................................................................... 1 ? changed yka (dsbga) package status to production data ................................................................................................ 1 ? added accuracy for 1.825 v in electrical characteristics table ............................................................................................. 5 ? changed output current limit in electrical characteristics table ............................................................................................ 5 ? added output current limit for +85 c in electrical characteristics table ................................................................................ 5 ? changed short-circuit current limit in electrical characteristics table .................................................................................... 5 ? added dropout voltage for 1.825 v in electrical characteristics table ................................................................................... 5 ? changed y-axis scaling and added conditions for i out transient 0 ma to 100 ma figure ..................................................... 7 ? changed y-axis scaling and added conditions for i out transient 0 ma to 200 ma figure .................................................... 8 ? added i out transient 0 ma to 50 ma figure to i out transient 3 a to 3 ma figure ............................................................... 8 ? added slew rate condition to v in transient figures (i out = 100 ma and i out = 200 ma) ....................................................... 9 ? added v in transient figures (i out = 150 ma and i out = 20 ma) .......................................................................................... 10 ? added v in condition to psrr vs frequency and i out figure (v out = 1.8 v) ........................................................................ 13 changes from original (february 2018) to revision a page ? released to production .......................................................................................................................................................... 1 3 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions dqn package 1-mm 1-mm, 4-pin x2son top view dbv package 5-pin sot-23 top view yka package 4-pin dsbga, 0.35-mm pitch top view yka package 4-pin dsbga, 0.35-mm pitch bottom view pin functions pin i/o description name dqn dbv yka in 4 1 a1 input input pin. for best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from in to ground as listed in the recommended operating conditions table. place the input capacitor as close to input of the device as possible. en 3 3 b1 input enable pin. driving this pin to logic high enables the device; driving this pin to logic low disables the device. if enable functionality is not required, this pin must be connected to in. v en must not exceed v in . gnd 2 2 b2 ? ground pin. this pin must be connected to ground on the board. out 1 5 a2 output regulated output pin. a capacitor is required from out to ground for stability. for best transient response, use the nominal recommended value or larger ceramic capacitor from out to ground. follow the recommended capacitor value as listed in the recommended operating conditions table. place the output capacitor as close to output of the device as possible. nc ? 4 ? ? no connect pin. this pin is not internally connected. connect to ground or leave floating. thermal pad pad ? ? ? connect the thermal pad to a large-area ground plane. this pad is not an electrical connection to the device ground. 1 out 2 gnd pad 3 en 4 in not to scale 1 2 b a not to scale en gnd in out 1 in 2 gnd 3 en 4 nc 5 out not to scale 1 2 a b not to scale in out en gnd 4 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages with respect to gnd. (3) v in + 0.3 v or 3.6 v (whichever is smaller) 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit voltage (2) in ? 0.3 6.0 v en ? 0.3 v in + 0.3 out ? 0.3 v in + 0.3 or 3.6 (3) current maximum output current internally limited a temperature operating junction temperature, t j ? 40 125 c storage temperature, t stg ? 65 150 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 1000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 500 (1) output current of 10 a minimum required to meet output voltage accuracy specification. 6.3 recommended operating conditions min nom max unit v in input supply voltage 1.4 5.5 v v en enable supply voltage 0 v in v v out nominal output voltage range 0.8 3.3 v i out output current (1) 0 200 ma c in input capacitor 1 f c out output capacitor 0.47 1 22 f t j operating junction temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) tps7a05 unit dbv (sot-23) dqn (x2son) yka (dsbga) 5 pins 4 pins 4 pins r ja junction-to-ambient thermal resistance 185.6 144.1 198.0 c/w r jc(top) junction-to-case (top) thermal resistance 104.3 137.9 2.1 c/w r jb junction-to-board thermal resistance 54.5 83.5 66.9 c/w jt junction-to-top characterization parameter 31.0 5.3 0.9 c/w y jb junction-to-board characterization parameter 54.5 83.8 76.0 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a 71.8 n/a c/w 5 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) i out 10 a required to meet accuracy specifications. (2) v in = 1.4 v for v out 0.9 v. (3) load regulation is normalized to the output voltage at i out = 1 ma. (4) dropout is measured by ramping v in down until v out = v out (nom) ? 5%. 6.5 electrical characteristics specified at t j = ? 40 c to +125 c, v in = v out(nom) + 0.5 v or 1.4 v (whichever is greater), i out = 1 ma, v en = v in , c in = 1 f, and c out = 1 f (unless otherwise noted); typical values are at t j = 25 c. parameter test conditions min typ max unit nominal accuracy (1) v out 1.0 v, t j = 25 c ? 1% 1% v out < 1.0 v, t j = 25 c ? 10 10 mv accuracy over temperature (1) v out 1.0 v, t j = ? 40 c to +85 c ? 2% 2% v out 1.0 v ? 3% 3% v out < 1.0 v, t j = ? 40 c to +85 c ? 20 20 mv v out < 1.0 v ? 30 30 v out = 1.825 v, t j = +10 to +45 , i out = 100 a ? 0.9% 0.9% v out( vin) line regulation v out(nom) + 0.5 v v in 5.5 v (2) , t j = ? 40 c to +85 c 5 16.5 mv v out(nom) + 0.5 v v in 5.5 v (2) 18 mv v out( iout) load regulation (3) 100 a i out 200 ma, v in = v out(nom) + v do(max) + 0.1 v, t j = ? 40 c to +85 c 20 43 mv 100 a i out 200 ma, v in = v out(nom) + v do(max) + 0.1 v 55 mv i gnd ground current t j = 25 c, i out = 1 a 0.6 1 1.3 a i out = 1 a, t j = ? 40 c to +85 c 2 i out = 1 a 3 i shdn shutdown current v en = 0.4 v, 1.4 v v in 5.5 v, t j = 25 c 100 300 na i cl output current limit v out = 90% v out(nom) , v in = v out(nom) + v do(max) + 0.5 v 210 450 700 ma i cl output current limit v out = 90% v out(nom) , v in = v out(nom) + v do(max) + 0.5 v, t j = 0 c to +85 c 250 450 700 ma i sc short-circuit current limit v out = 0 v 65 150 ma v do dropout voltage (4) i out = 200 ma, t j = ? 40 c to +85 c 0.8 v v out < 1.0 v 915 mv 1.0 v v out < 1.2 v 758 1.2 v v out < 1.5 v 609 1.5 v v out < 1.8 v 469 1.8 v v out < 2.5 v 341 2.5 v v out < 3.3 v 275 v out = 3.3 v 212 i out = 200 ma 0.8 v v out < 1.0 v 1004 1.0 v v out < 1.2 v 837 1.2 v v out < 1.5 v 679 1.5 v v out < 1.8 v 525 1.8 v v out < 2.5 v 382 2.5 v v out < 3.3 v 308 v out = 3.3 v 235 i out = 100 a, t j = +10 to +45 v out = 1.825 v 20 mv 6 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) specified at t j = ? 40 c to +125 c, v in = v out(nom) + 0.5 v or 1.4 v (whichever is greater), i out = 1 ma, v en = v in , c in = 1 f, and c out = 1 f (unless otherwise noted); typical values are at t j = 25 c. parameter test conditions min typ max unit psrr power-supply rejection ratio f = 1 khz, i out = 30 ma 40 db f = 500 khz, i out = 30 ma 30 f = 1 mhz, i out = 30 ma 40 v n output voltage noise bw = 10 hz to 100 khz, v out = 1.2 v, i out = 30 ma 180 v rms v uvlo uvlo threshold v in rising 1.21 1.3 1.37 v v uvlo(hyst) uvlo hysteresis v in falling 40 mv v uvlo uvlo threshold v in falling 1.17 1.33 v v en(hi) en pin logic high voltage 0.9 v v en(lo) en pin logic low voltage 0.4 v i en en pin current v en = v in = 5.5 v 10 na r pulldown pulldown resistor v in = 3.3 v, p version only 120 t sd thermal shutdown temperature shutdown, temperature increasing 160 c reset, temperature decreasing 140 (1) see the special considerations when ramping down in and enable section for details on minimum ramp down rates to ensure specified start-up time. 6.6 switching characteristics specified at t j = ? 40 to +125 c, v in = v out(nom) + v do(max) + 0.5 v, i out = 10 ma, c in = 1 f, and c out = 1 f (unless otherwise noted); typical values are at t j = 25 c. parameter test conditions min typ max unit t str start-up time (1) from en assertion to v out = 95% v out(nom) , v out = 1.8 v 1.5 2.8 ms 7 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.7 typical characteristics at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 2.0 v (whichever is greater), i out = 1 ma, v en = v in , c in = 1 f, and c out = 1 f (unless otherwise noted) figure 1. i q vs v in and temperature v en < 0.4 v figure 2. i shdn vs v in and temperature v en < 0.4 v figure 3. i shdn vs v in and temperature figure 4. i gnd vs i out up to 10 ma figure 5. i gnd vs i out up to 200 ma output current slew rate = 3.3 ma/ s figure 6. i out transient 0 ma to 100 ma input voltage (v) quiescent current ( p a) 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0.5 0.75 1 1.25 1.5 1.75 2 2.25 d001 t j -40c 0c 25c 85c 125c input voltage (v) quiescent current in shutdown (na) 1.5 2 2.5 3 3.5 4 4.5 5 5.5 50 100 150 200 250 300 350 400 450 500 550 d002 t j -40c 0c 25c 85c input voltage (v) quiescent current in shutdown (na) 1.5 2 2.5 3 3.5 4 4.5 5 5.5 1000 1500 2000 2500 3000 3500 d044 t j 125c output current (ma) ground current ( p a) 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 d042 output current (ma) ground current ( p a) 0 20 40 60 80 100 120 140 160 180 200 0 1 2 3 4 5 6 7 d043 time (s) ac-coupled output voltage (mv) output current (ma) 0 100 200 300 400 500 600 700 800 900 1000 -900 -50 -800 0 -700 50 -600 100 -500 150 -400 200 -300 250 -200 300 -100 350 0 400 100 450 200 500 300 550 d036 v out i out 8 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 2.0 v (whichever is greater), i out = 1 ma, v en = v in , c in = 1 f, and c out = 1 f (unless otherwise noted) output current slew rate = 6.6 ma/ s figure 7. i out transient 0 ma to 200 ma output current slew rate = 50 ma/ s figure 8. i out transient 0 ma to 50 ma output current slew rate = 100 ma/ s figure 9. i out transient 0 ma to 100 ma output current slew rate = 150 ma/ s figure 10. i out transient 0 ma to 150 ma output current slew rate = 200 ma/ s figure 11. i out transient 0 ma to 200 ma output current slew rate = 50 ma/ s figure 12. i out transient 1 ma to 50 ma time (s) ac-coupled output voltage (mv) output current (ma) 0 100 200 300 400 500 600 700 800 900 1000 -900 -50 -800 0 -700 50 -600 100 -500 150 -400 200 -300 250 -200 300 -100 350 0 400 100 450 200 500 300 550 d008 v out i out time (s) ac-coupled output voltage (mv) output current (ma) 0 50 100 150 200 250 300 350 400 450 500 -900 -50 -800 0 -700 50 -600 100 -500 150 -400 200 -300 250 -200 300 -100 350 0 400 100 450 200 500 300 550 d045 v out i out time (s) ac-coupled output voltage (mv) output current (ma) 0 50 100 150 200 250 300 350 400 450 500 -1800 -50 -1600 0 -1400 50 -1200 100 -1000 150 -800 200 -600 250 -400 300 -200 350 0 400 200 450 400 500 600 550 d047 v out i out time (s) ac-coupled output voltage (mv) output current (ma) 0 50 100 150 200 250 300 350 400 450 500 -900 -50 -800 0 -700 50 -600 100 -500 150 -400 200 -300 250 -200 300 -100 350 0 400 100 450 200 500 300 550 d046 v out i out time (s) ac-coupled output voltage (mv) output current (ma) 0 50 100 150 200 250 300 350 400 450 500 -900 -50 -800 0 -700 50 -600 100 -500 150 -400 200 -300 250 -200 300 -100 350 0 400 100 450 200 500 300 550 d049 v out i out time (s) ac-coupled output voltage (mv) output current (ma) 0 50 100 150 200 250 300 350 400 450 500 -1800 -50 -1600 0 -1400 50 -1200 100 -1000 150 -800 200 -600 250 -400 300 -200 350 0 400 200 450 400 500 600 550 d048 v out i out 9 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 2.0 v (whichever is greater), i out = 1 ma, v en = v in , c in = 1 f, and c out = 1 f (unless otherwise noted) output current slew rate = 100 ma/ s figure 13. i out transient 1 ma to 100 ma output current slew rate = 150 ma/ s figure 14. i out transient 1 ma to 150 ma output current slew rate = 200 ma/ s figure 15. i out transient 1 ma to 200 ma c in = c out = 10 f, output current slew rate = 3 ma/ s figure 16. i out transient 3 a to 3 ma i out = 100 ma, input voltage slew rate = 0.6 v/ s figure 17. v in transient i out = 200 ma, input voltage slew rate = 0.6 v/ s figure 18. v in transient time (s) ac-coupled output voltage (mv) output current (ma) 0 50 100 150 200 250 300 350 400 450 500 -900 -50 -800 0 -700 50 -600 100 -500 150 -400 200 -300 250 -200 300 -100 350 0 400 100 450 200 500 300 550 exced050 v out i out time (s) ac-coupled output voltage (mv) output current (ma) 0 50 100 150 200 250 300 350 400 450 500 -1800 -50 -1600 0 -1400 50 -1200 100 -1000 150 -800 200 -600 250 -400 300 -200 350 0 400 200 450 400 500 600 550 d051 v out i out time (s) ac-coupled output voltage (mv) change in input voltage (mv) 0 100 200 300 400 500 600 700 800 900 1000 -500 -300 -400 0 -300 300 -200 600 -100 900 0 1200 100 1500 200 1800 300 2100 d012 v out v in time (s) ac-coupled output voltage (mv) output current (ma) 0 50 100 150 200 250 300 350 400 450 500 -1800 -50 -1600 0 -1400 50 -1200 100 -1000 150 -800 200 -600 250 -400 300 -200 350 0 400 200 450 400 500 600 550 d052 v out i out time (s) ac-coupled output voltage (mv) change in input voltage (mv) 0 100 200 300 400 500 600 700 800 900 1000 -500 -300 -400 0 -300 300 -200 600 -100 900 0 1200 100 1500 200 1800 300 2100 d011 v out v in time (ms) ac-coupled output voltage (mv) output current (ma) 0 20 40 60 80 100 120 140 160 180 200 -50 -10 -40 0 -30 10 -20 20 -10 30 0 40 10 50 20 60 30 70 d053 v out i out 10 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 2.0 v (whichever is greater), i out = 1 ma, v en = v in , c in = 1 f, and c out = 1 f (unless otherwise noted) i out = 150 ma, input voltage slew rate = 0.1 v/ s figure 19. v in transient i out = 20 ma, input voltage slew rate = 0.01 v/ s figure 20. v in transient v out = 1.8 v figure 21. dropout vs i out and temperature v out = 3.3 v figure 22. dropout vs i out and temperature figure 23. dropout vs v in and temperature v out = 0.8 v figure 24. line regulation v in and temperature input voltage (v) dropout voltage (mv) 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 0 100 200 300 400 500 600 d027 t j -40c 0c 25c 85c 125c input voltage (v) change in output voltage (mv) 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -1 0 1 2 3 4 5 6 7 8 9 10 d009 t j -40c 0c 25c 85c 125c load current (ma) dropout voltage (mv) 0 25 50 75 100 125 150 175 200 0 100 200 300 400 500 600 d013 t j -40c 0c 25c 85c 125c load current (ma) dropout voltage (mv) 0 25 50 75 100 125 150 175 200 0 100 200 300 400 500 600 d014 t j -40c 0c 25c 85c 125c time (s) ac-coupled output voltage (mv) change in input voltage (mv) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 -250 -500 -200 0 -150 500 -100 1000 -50 1500 0 2000 50 2500 100 3000 150 3500 d055 v out v in time (s) ac-coupled output voltage (mv) change in input voltage (mv) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 -500 -500 -400 0 -300 500 -200 1000 -100 1500 0 2000 100 2500 200 3000 300 3500 d054 v out v in 11 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 2.0 v (whichever is greater), i out = 1 ma, v en = v in , c in = 1 f, and c out = 1 f (unless otherwise noted) v out = 0.8 v figure 25. output accuracy v in and temperature v out = 1.8 v figure 26. line regulation v in and temperature v out = 1.8 v figure 27. output accuracy v in and temperature v out = 1.8 v figure 28. load regulation vs i out and temperature v out = 1.8 v figure 29. foldback current limit vs i out and temperature v out = 0.8 v, i out = 1 ma figure 30. startup with v en = v in output current (ma) change in output voltage (mv) 0 20 40 60 80 100 120 140 160 180 200 -30 -24 -18 -12 -6 0 6 t j -40c 0c 25c 85c 125c input voltage (v) output voltage accuracy ( ) 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 d006 t j -40c 0c 25c 85c 125c input voltage (v) output voltage accuracy ( ) 2 2.5 3 3.5 4 4.5 5 5.5 -0.2 0 0.2 0.4 0.6 0.8 1 d005 t j -40c 0c 25c 85c 125c input voltage (v) change in output voltage (mv) 2 2.5 3 3.5 4 4.5 5 5.5 -2 0 2 4 6 8 10 12 14 d004 t j -40c 0c 25c 85c 125c time (ms) voltage (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 d029 v en v in v out output current (ma) output voltage (v) 0 50 100 150 200 250 300 350 400 450 500 0 0.5 1 1.5 2 2.5 d003 t j -40c 0c 25c 85c 12 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 2.0 v (whichever is greater), i out = 1 ma, v en = v in , c in = 1 f, and c out = 1 f (unless otherwise noted) v out = 0.8 v, i out = 30 ma figure 31. startup with v en = v in v out = 1.8 v, i out = 30 ma figure 32. startup with v en = v in v out = 0.8 v, i out = 1 ma figure 33. startup with separate v in and v en v out = 0.8 v, i out = 30 ma figure 34. startup with separate v in and v en v out = 1.8 v, i out = 30 ma figure 35. startup with separate v in and v en v out = 0.8 v, i out = 200 ma, c out = 1 f, c in = 0 f figure 36. psrr vs frequency and v in frequency (hz) power supply rejection ratio (db) 5 10 15 20 25 30 35 40 45 50 55 60 10 100 1k 10k 100k 1m 10m d022 v in 1.4 v 1.5 v 1.6 v 1.8 v time (ms) voltage (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 d032 v en v in v out time (ms) voltage (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 d034 v en v in v out time (ms) voltage (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 d030 v en v in v out time (ms) voltage (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 d033 v en v in v out time (ms) voltage (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 d031 v en v in v out 13 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 2.0 v (whichever is greater), i out = 1 ma, v en = v in , c in = 1 f, and c out = 1 f (unless otherwise noted) v out = 1.8 v, i out = 200 ma, c out = 1 f, c in = 0 f figure 37. psrr vs frequency and v in v out = 3.3 v, i out = 200 ma, c out = 1 f, c in = 0 f figure 38. psrr vs frequency and v in v out = 0.8 v, v in = 1.4 v, c out = 1 f, c in = 0 f figure 39. psrr vs frequency and i out v out = 1.8 v, v in = 2.8 v, c out = 1 f, c in = 0 f figure 40. psrr vs frequency and i out v out = 3.3 v, v in = 3.8 v, c out = 1 f, c in = 0 f figure 41. psrr vs frequency and i out v out = 1.8 v, i out = 200 ma, c out = 1 f figure 42. output noise vs frequency and v in frequency (hz) power supply rejection ratio (db) 0 5 10 15 20 25 30 35 40 45 50 55 10 100 1k 10k 100k 1m 10m d016 v in 2.2 v 2.3 v 2.4 v 2.5 v 2.8 v 3.3 v 3.6 v frequency (hz) power supply rejection ratio (db) 0 10 20 30 40 50 60 10 100 1k 10k 100k 1m 10m d020 v in 3.6 v 3.8 v 4.0 v 4.2 v 4.6 v frequency (hz) power supply rejection ratio (db) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 10 100 1k 10k 100k 1m 10m d019 i out 0 ma 10 ma 50 ma 100 ma 150 ma 200 ma frequency (hz) output voltage noise ( p v ? hz) 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 2020 10 100 1k 10k 100k 1m 10m d025 v in 2.2 v 2.8 v 3.3 v 5.5 v frequency (hz) power supply rejection ratio (db) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 10 100 1k 10k 100k 1m 10m d021 i out 0 ma 10 ma 50 ma 100 ma frequency (hz) power supply rejection ratio (db) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 10 100 1k 10k 100k 1m 10m d015 i out 0 ma 10 ma 50 ma 100 ma 150 ma 200 ma 14 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 2.0 v (whichever is greater), i out = 1 ma, v en = v in , c in = 1 f, and c out = 1 f (unless otherwise noted) v out = 1.8 v, v in = 2.8 v, c out = 1 f figure 43. output noise vs frequency and i out v out = 1.8 v, v in = 2.8 v, i out = 200 ma figure 44. output noise vs frequency and c out v in = v out + 1 v, i out = 200 ma, c out = 1 f figure 45. output noise vs frequency and v out figure 46. uvlo v in rising and falling thresholds vs temperature figure 47. enable high and low thresholds vs temperature temperature ( q c) enable voltage (v) -40 -20 0 20 40 60 80 100 120 140 0.54 0.56 0.58 0.6 0.62 0.64 0.66 0.68 d037 v en(hi) v en(lo) frequency (hz) output voltage noise ( p v ? hz) 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 2020 10 100 1k 10k 100k 1m 10m d028 v out 0.8 v 1.8 v 3.3 v frequency (hz) output voltage noise ( p v ? hz) 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 10 100 1k 10k 100k 1m 10m d026 c out 1.0 f 10 f frequency (hz) output voltage noise ( p v ? hz) 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 2020 10 100 1k 10k 100k 1m 10m d024 i out 50 ma 100 ma 150 ma 200 ma temperature ( q c) input voltage (v) -40 -20 0 20 40 60 80 100 120 140 1.22 1.24 1.26 1.28 1.3 d035 v uvlo, rising v uvlo, falling 15 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the tps7a05 is a ultra-low i q linear voltage regulator that is optimized for excellent transient performance. these characteristics make the tps7a05 ideal for most battery-powered applications. this low-dropout regulator (ldo) offers foldback current limit, shutdown, thermal protection, and optional active discharge. 7.2 functional block diagram + current limit 1.2-v bandgap thermal shutdown error amp internal controller out en in gnd active discharge p-version only + uvlo 16 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3 feature description 7.3.1 excellent transient response the device includes several innovative circuits to ensure excellent transient response. dynamic biasing increases the i q for a short duration during transients to extend the closed-loop bandwidth and improve the device response time during transients. adaptive biasing increases the i q as the dc load current increases, extending the bandwidth of the control loop. the device response time across the output voltage range is constant because of the use of a buffered reference topology, which keeps the control loop in unity gain at any output voltage. these features give the device a wide loop bandwidth during transients that ensure excellent transient response while maintaining the device low i q in steady-state conditions; see the application and implementation section for more details. 7.3.2 active discharge devices with this option have an internal pulldown mosfet that connects a 120- resistor to ground when the device is disabled to actively discharge the output voltage. the active discharge circuit is activated when the device is disabled, in undervoltage lockout (uvlo), or in thermal shutdown. the discharge time after disabling depends on the output capacitance (c out ) and the load resistance (r l ) in parallel with the 120- pulldown resistor. equation 1 calculates the time constant: (1) do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. this reverse current flow can cause damage to the device. limit reverse current to no more than 5% of the device-rated current. 7.3.3 low i q in dropout in most ldos the i q significantly increases when the device is placed into dropout, which is especially true for low i q ldos with adaptive biasing. the tps7a05 detects when operating in dropout and disables the adaptive biasing, minimizing the i q increase. 7.3.4 undervoltage lockout (uvlo) the undervoltage lockout (uvlo) circuit monitors the input voltage (v in ) to prevent the device from turning on before v in rises above the lockout voltage. the uvlo circuit also disables the output of the device when v in falls below the lockout voltage. if the device includes the optional active discharge, the output is connected to ground with a 120- pulldown resistor when v in is below the lockout voltage; see the application and implementation section for more details. 7.3.5 enable the enable pin for the device is active high. the output of the device is turned on when the enable pin voltage is greater than the en pin logic high voltage, and the output of the device is turned off when the enable pin voltage is less than the en pin logic low voltage. a voltage less than the en pin logic low voltage on the enable pin disables all internal circuits. at the next turn-on, any voltage on the en pin below the logic low voltage ensures a normal start-up waveform with start-up ramp rate control, provided there is enough time to discharge the output capacitance. if shutdown capability is not required, connect en to in. v en must not exceed v in . 7.3.6 internal foldback current limit the internal foldback current-limit circuit is used to protect the ldo against high-load current faults or shorting events. the foldback mechanism lowers the current limit as the output voltage decreases, and limits power dissipation during short-circuit events while still allowing for the device to operate at its rated output current; see figure 29 . t = 120 r l 120 + r l c out 17 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) a foldback example for this device is that when v out is 90% of v out(nom) the current limit is i cl (typical); however, if v out is forced to 0 v the current limit is i sc (typical). in many ldos the foldback current limit can prevent start-up into a constant-current load or a negatively-biased output. the foldback mechanism for this device goes into a brick-wall current limit when v out > 500 mv (typ), thus limiting current to i cl (typical) and, when v out is approximately 0 v, current is limited to i sc (typical) to ensure normal start-up into a variety of loads. the foldback current limit is disengaged when i out < 1 ma (typical) to reduce i q . as such, the current-limit loop takes longer to respond to a current-limit event when i out < 1 ma (typ). thermal shutdown can activate during a current-limit event because of the high power dissipation typically found in these conditions. to ensure proper operation of the current limit, minimize the inductances to the input and load. continuous operation in current limit is not recommended. 7.3.7 thermal shutdown the device contains a thermal shutdown protection circuit to disable the device when thermal junction temperature (t j ) of the main pass-fet rises to t sd(shutdown) (typical). thermal shutdown hysteresis assures that the ldo resets again (turns on) when the temperature falls to t sd(reset) (typical). the thermal time-constant of the semiconductor die is fairly short, and thus the device may cycle on and off when thermal shutdown is reached until power dissipation is reduced. for reliable operation, limit the junction temperature to a maximum of 125 c. operation above 125 c causes the device to exceed its operational specifications. although the internal protection circuitry of the device is designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking. continuously running the device into thermal shutdown or above a junction temperature of 125 c reduces long- term reliability. a fast start-up when t j > t sd(reset) (typical, outside of the specified operating range) causes the device thermal shutdown to assert at t sd(reset) and prevents the device from turning on until the junction temperature is reduced below t sd(shutdown) . 18 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4 device functional modes the device has several modes of operation,: ? normal operation: the device regulates to the nominal output voltage ? dropout operation: the pass element operates as a resistor and the output voltage is set as v in ? v do ? shutdown: the output of the device is disabled and the discharge circuit is activated table 1 shows the conditions that lead to the different modes of operation. see the electrical characteristics table for parameter values. table 1. device functional mode comparison operating mode parameter v in v en i out t j normal mode v in > v out(nom) + v do and v in > v in(min) v en > v en(hi) i out < i out(max) t j < t sd(shutdown) dropout mode v in(min) < v in < v out(nom) + v do v en > v en(hi) i out < i out(max) t j < t sd(shutdown) disabled mode (any true condition disables the device) v in < v uvlo v en < v en(lo) ? t j > t sd(shutdown) 7.4.1 normal mode the device regulates the output to the nominal output voltage when all normal mode conditions in table 1 are met. 7.4.2 dropout mode the device is not in regulation, and the output voltage tracks the input voltage minus the voltage drop across the pass transistor of the device. in this mode, the psrr, noise, and transient performance of the device are significantly degraded. 7.4.3 disable mode in this mode, the pass element is turned off, the internal circuits are shut down, and the output voltage is actively discharged to ground by an internal resistor. 19 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information 8.1.1 recommended capacitor types the device is designed to be stable using low equivalent series resistance (esr) ceramic capacitors at the input and output. multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. ceramic capacitors that employ x7r-, x5r-, and cog-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of y5v-rated capacitors is discouraged because of large variations in capacitance. regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. as a rule of thumb, assume effective capacitance to decrease by as much as 50%. the input and output capacitors recommended in the recommended operating conditions table account for an effective capacitance of approximately 50% of the nominal value. 8.1.2 input and output capacitor requirements although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from in to gnd. this capacitor counteracts reactive input sources and improves transient response, input ripple, and psrr. an input capacitor is recommended if the source impedance is more than 0.5 . a higher value capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. dynamic performance of the device is improved with the use of an output capacitor. use an output capacitor within the range specified in the recommended operating conditions table for stability. 8.1.3 special considerations when ramping down v in and enable care must be taken when ramping down voltage on the in and en pins to power-down the device when the operating free-air temperature is less than 15 c. the minimum ramp-down time for the in pin is 10 ms. the minimum ramp-down time for the en pin is 100 s. ramping at faster rates can cause the regulator to exhibit undesired startup behavior on the next power-on. if v in is ramped down faster than 10 ms, the next startup may exhibit a partial startup, shutoff, followed by a normal soft-start startup. figure 48 shows this response. figure 48. partial startup, shutdown, normal startup with v en = v in time (ms) voltage (v) 0 1 2 3 4 5 6 7 8 9 10 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 d040 v en v in v out 20 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) if the en pin is ramped down faster than 100 s, the next startup may exhibit a delay time of up to 130 ms before the output ramps up with a normal soft-start startup. figure 49 shows this delay. figure 49. long delay to startup with v en = v in fast ramp downs of v in and the en pin charge internal high-impedance nodes in the device, which take extended time to discharge below 15 c. to avoid these startup behaviors, follow the recommended minimum ramp down times for v in and the en pin. 8.1.4 load transient response the load-step transient response is the output voltage response by the ldo to a step in load current, whereby output voltage regulation is maintained. see figure 6 for typical load transient response. there are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. the regions in figure 50 are broken down as described in this section. regions a, e, and h are where the output voltage is in steady-state. during transitions from a light load to a heavy load, the: ? initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the output capacitor (region b) ? recovery from the dip results from the ldo increasing its sourcing current, and leads to output voltage regulation (region c) during transitions from a heavy load to a light load, the: ? initial voltage rise results from the ldo sourcing a large current, and leads to the output capacitor charge to increase (region f) ? recovery from the rise results from the ldo decreasing its sourcing current in combination with the load discharging the output capacitor (region g) a larger output capacitance reduces the peaks during a load transient but slows down the response time of the device. a larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher current discharge path is provided for the output capacitor. figure 50. load transient waveform time (ms) voltage (v) 0 100 200 300 400 500 600 700 800 900 1000 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 d041 v out v in t a t t d t t e t t c t t g t t h t f b 21 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) 8.1.5 dropout voltage the device uses a pmos pass transistor to achieve low dropout. when (v in ? v out ) is less than the dropout voltage (v do ), the pmos pass transistor is in the linear region of operation, and the input-to-output resistance of the device is the drain-to-source resistance of the pmos pass transistor. v do scales with the output current and changes with temperature because the pmos pass transistor functions like a resistor in dropout mode. for a graph of dropout voltage, see figure 22 . as with any linear regulator, psrr and the transient response degrade as (v in ? v out ) approaches dropout operation. see figure 23 for dropout performance. 8.1.5.1 behavior when transitioning from dropout into regulation some applications may have transients that place the device into dropout, especially as this device can be powered from a battery with high esr. a typical application with these conditions is using a stack of two 1.55-v coin-cell batteries with an esr of 30 to create a 2.5-v rail and experiencing a load transient from 1 a to 25 ma. this load transient causes the input supply to drop 750 mv, placing the device into dropout. the load transient saturates the output stage of the error amplifier when the pass element is driven fully on, making the pass element function like a resistor from v in to v out . the error amplifier response time to this load transient is limited because the error amplifier must first recover from saturation and then place the pass element back into active mode. during this time v out overshoots because the pass element is functioning as a resistor from v in to v out . this device uses a loop pulldown circuit to help mitigate the overshoot. if operating under these conditions, applying a higher dc load or increasing the output capacitance reduces the overshoot because these solutions provide a path to dissipate the excess charge. 8.1.5.2 behavior of output resulting from line transient when in dropout the output deviation resulting from a line transient can be significantly higher when the device is operating in dropout. as explained in the dropout voltage section, the response time of the error amplifier is limited when in dropout, so the output deviation is larger and can exceed twice the regulated output voltage. care must be taken in applications where line transients are expected when the device is operating in dropout. 8.1.6 undervoltage lockout (uvlo) operation the uvlo circuit ensures that the device stays disabled before its input supply reaches the minimum operational voltage range, and ensures that the device shuts down when the input supply collapses. see figure 46 for rising and falling thresholds. figure 51 depicts the uvlo circuit response to various input voltage events. the diagram can be separated into the following parts: ? region a: the device does not start until the input reaches the uvlo rising threshold ? region b: normal operation, regulating device ? region c: brownout event above the uvlo falling threshold (uvlo rising threshold ? uvlo hystersis). the output may fall out of regulation but the device is still enabled. ? region d: normal operation, regulating device ? region e: brownout event below the uvlo falling threshold. the device is disabled in most cases and the output falls as a result of the load and active discharge circuit. the device is re-enabled when the uvlo rising threshold is reached by the input voltage and a normal start-up follows. ? region f: normal operation followed by the input falling to the uvlo falling threshold ? region g: the device is disabled as the input voltage falls below the uvlo falling threshold to 0 v. the output falls as a result of the load and active discharge circuit. 22 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) figure 51. typical uvlo operation 8.1.7 power dissipation (p d ) circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (pcb), and correct sizing of the thermal plane. the pcb area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses. equation 2 calculates the maximum allowable power dissipation for the device in a given package: p d-max = ((t j ? t a ) / r ja ) (2) equation 3 represents the actual power being dissipated in the device: p d = (v in - v out ) i out (3) an important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. proper selection allows the minimum input-to-output voltage differential to be obtained. the low dropout of the tps7a05 allows for maximum efficiency across a wide range of output voltages. the main heat conduction path for the device depends on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air. the maximum power dissipation determines the maximum allowable junction temperature (t j ) for the device. according to equation 4 , maximum power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (r ja ) of the combined pcb and device package and the temperature of the ambient air (t a ). the equation is rearranged in equation 5 for output current. t j = t a + (r ja p d ) (4) i out = (t j ? t a ) / [r ja (v in ? v out )] (5) unfortunately, this thermal resistance (r ja ) is highly dependent on the heat-spreading capability built into the particular pcb design, and therefore varies according to the total copper area, copper weight, and location of the planes. the r ja recorded in the thermal information table is determined by the jedec standard, pcb, and copper-spreading area, and is only used as a relative measure of package thermal performance. for a well- designed thermal layout, r ja is actually the sum of the dqn package junction-to-case (bottom) thermal resistance (r jc(bot) ) plus the thermal resistance contribution by the pcb copper. c t a t v in v out uvlo rising threshold uvlo hysteresis t b t t d t t e t t f t t g t 23 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) 8.1.7.1 estimating junction temperature the jedec standard now recommends the use of psi ( ) thermal metrics to estimate the junction temperatures of the ldo when in-circuit on a typical pcb board application. these metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. these psi metrics are determined to be significantly independent of the copper-spreading area. the key thermal metrics ( jt and jb ) are used in accordance with equation 6 and are given in the thermal information table. jt : t j = t t + jt p d and jb : t j = t b + jb p d where: ? p d is the power dissipated as explained in equation 3 ? t t is the temperature at the center-top of the device package, and ? t b is the pcb surface temperature measured 1 mm from the device package and centered on the package edge (6) 8.1.7.2 recommended area for continuous operation the operational area of an ldo is limited by the dropout voltage, output current, junction temperature, and input voltage. the recommended area for continuous operation for a linear regulator is shown in figure 52 and can be separated into the following regions: ? dropout voltage limits the minimum differential voltage between the input and the output (v in ? v out ) at a given output current level; see the dropout voltage section for more details. ? the rated output currents limits the maximum recommended output current level. exceeding this rating causes the device to fall out of specification. ? the rated junction temperature limits the maximum junction temperature of the device. exceeding this rating causes the device to fall out of specification and reduces long-term reliability. ? equation 5 provides the shape of the slope. the slope is nonlinear because the maximum rated junction temperature of the ldo is controlled by the power dissipation across the ldo, thus when v in ? v out increases the output current must decrease. ? the rated input voltage range governs both the minimum and maximum of v in ? v out . figure 52. region description for continuous operation rated output current output current limited by dropout output current limited by thermals limited by minimum v in limited by maximum v in v in v out (v) output current (a) 24 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2 typical application figure 53. operation from the battery input supply 8.2.1 design requirements table 2 summarizes the design requirements for figure 53 . table 2. design parameters parameter design requirement input voltage 3.0 v to 2.0 v (cr2032 battery) output voltage 1.0 v, 2% (t j from ? 40 to +85 o c) output load 10 ma 8.2.2 design considerations for this design example, the 1.0-v, fixed-version tps7a0510 device is selected. a single cr2032 coin-cell battery was used, thus a 1.0- f input capacitor is recommended to minimize transient currents drawn from the battery. a 1.0- f output capacitor is also recommended for excellent load transient response. the dropout voltage (v do ) is kept within the tps7a05 dropout voltage specification for the 1.0-v output voltage option to keep the device in regulation under all load and temperature conditions for this design. the very small ground current consumed by the regulator shown in figure 54 allows for long battery life. 8.2.3 application curve figure 54. i gnd vs i out at 25 c 9 power supply recommendations this device is designed to operate from an input supply voltage range of 1.4 v to 5.5 v. the input supply must be well regulated and free of spurious noise. to ensure that the output voltage is well regulated and dynamic performance is optimum, the input supply must be at least v out(nom) + 0.5 v. a 1 f or greater input capacitor is recommended to be used to reduce the impedance of the input supply, especially during transients. output current (ma) ground current ( p a) 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 d042 load v bat in out en gnd tps7a05 c in c out 25 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 layout 10.1 layout guidelines ? place input and output capacitors as close to the device as possible ? use copper planes for device connections to optimize thermal performance ? place thermal vias around the device to distribute heat ? do not place a thermal via directly beneath the thermal pad of the dqn package. a via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad. 10.2 layout example figure 55. layout example for the yka package figure 56. layout example for the dbv package figure 57. layout example for the dqn package c out v out v in gnd plane c in represents via used for application specific connections 1 23 4 5 en c out v out v in gnd plane c in represents via used for application specific connections 12 3 4 en c in c out out in gnd en a2 b2 a1 b1 via 26 tps7a05 sbvs254b ? february 2018 ? revised august 2018 www.ti.com product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for the most current package and ordering information see the package option addendum at the end of this document, or visit the device product folder on www.ti.com . (2) output voltages from 1.0 v to 3.3 v in 50-mv increments are available. contact the factory for details and availability. 11 device and documentation support 11.1 device support 11.1.1 spice models spice models for the tps7a05 are available through the product folder under tools & software . 11.1.2 device nomenclature table 3. device nomenclature (1) (2) product v out tps7a05 xx(x)pyyyz xx(x) is the nominal output voltage. for output voltages with a resolution of 100 mv, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 v; 125 = 1.25 v). p is optional; p indicates an active output discharge feature. yyy is the package designator. z is the package quantity. r is for reel (3000 pieces), t is for tape (250 pieces). 11.2 documentation support 11.2.1 related documentation for related documentation see the following: universal low-dropout (ldo) linear voltage regulator multipkgldoevm-823 evaluation module 11.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.5 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 27 tps7a05 www.ti.com sbvs254b ? february 2018 ? revised august 2018 product folder links: tps7a05 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. package option addendum www.ti.com 24-aug-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps7a0508pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1c6f tps7a0508pdbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1c6f TPS7A0508PDQNR active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 6g tps7a0508pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 6g tps7a0508pykar preview dsbga yka 4 12000 tbd call ti call ti -40 to 125 tps7a0510pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1ikf tps7a0510pdbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1ikf tps7a0510pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c7 tps7a0510pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c7 tps7a0510pykar preview dsbga yka 4 12000 tbd call ti call ti -40 to 125 tps7a0512pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1ilf tps7a0512pdbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1ilf tps7a0512pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c8 tps7a0512pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c8 tps7a0512pykar preview dsbga yka 4 12000 tbd call ti call ti -40 to 125 tps7a0515pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1imf tps7a0515pdbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1imf tps7a0515pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c9 package option addendum www.ti.com 24-aug-2018 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps7a0515pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c9 tps7a0515pykar preview dsbga yka 4 12000 tbd call ti call ti -40 to 125 tps7a051825pykar preview dsbga yka 4 12000 tbd call ti call ti -40 to 125 tps7a0518pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1inf tps7a0518pdbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1inf tps7a0518pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ca tps7a0518pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ca tps7a0518pykar preview dsbga yka 4 12000 tbd call ti call ti -40 to 125 tps7a0522pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1p3f tps7a0522pdbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1p3f tps7a0525pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1iof tps7a0525pdbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1iof tps7a0525pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cb tps7a0525pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cb tps7a0525pykar preview dsbga yka 4 12000 tbd call ti call ti -40 to 125 tps7a05285pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1irf tps7a05285pdbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1irf tps7a05285pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cc tps7a05285pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cc tps7a05285pykar preview dsbga yka 4 12000 tbd call ti call ti -40 to 125 package option addendum www.ti.com 24-aug-2018 addendum-page 3 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps7a0528pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dh tps7a0528pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dh tps7a0530pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dg tps7a0530pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dg tps7a0530pykar preview dsbga yka 4 12000 tbd call ti call ti -40 to 125 tps7a0531pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1p4f tps7a0531pdbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1p4f tps7a0533pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1ipf tps7a0533pdbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1ipf tps7a0533pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cd tps7a0533pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cd tps7a0533pykar preview dsbga yka 4 12000 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. package option addendum www.ti.com 24-aug-2018 addendum-page 4 (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps7a0508pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0508pdbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 TPS7A0508PDQNR x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0508pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0510pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0510pdbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0510pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0510pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0512pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0512pdbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0512pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0512pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0515pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0515pdbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0515pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0515pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0518pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0518pdbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 package materials information www.ti.com 2-aug-2018 pack materials-page 1 device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps7a0518pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0518pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0522pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0522pdbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0525pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0525pdbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0525pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0525pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a05285pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a05285pdbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a05285pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a05285pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0528pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0528pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0530pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0530pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0531pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0531pdbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0533pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0533pdbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tps7a0533pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tps7a0533pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 package materials information www.ti.com 2-aug-2018 pack materials-page 2 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps7a0508pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tps7a0508pdbvt sot-23 dbv 5 250 210.0 185.0 35.0 TPS7A0508PDQNR x2son dqn 4 3000 184.0 184.0 19.0 tps7a0508pdqnt x2son dqn 4 250 184.0 184.0 19.0 tps7a0510pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tps7a0510pdbvt sot-23 dbv 5 250 210.0 185.0 35.0 tps7a0510pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tps7a0510pdqnt x2son dqn 4 250 184.0 184.0 19.0 tps7a0512pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tps7a0512pdbvt sot-23 dbv 5 250 210.0 185.0 35.0 tps7a0512pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tps7a0512pdqnt x2son dqn 4 250 184.0 184.0 19.0 tps7a0515pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tps7a0515pdbvt sot-23 dbv 5 250 210.0 185.0 35.0 tps7a0515pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tps7a0515pdqnt x2son dqn 4 250 184.0 184.0 19.0 tps7a0518pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tps7a0518pdbvt sot-23 dbv 5 250 210.0 185.0 35.0 tps7a0518pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tps7a0518pdqnt x2son dqn 4 250 184.0 184.0 19.0 package materials information www.ti.com 2-aug-2018 pack materials-page 3 device package type package drawing pins spq length (mm) width (mm) height (mm) tps7a0522pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tps7a0522pdbvt sot-23 dbv 5 250 210.0 185.0 35.0 tps7a0525pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tps7a0525pdbvt sot-23 dbv 5 250 210.0 185.0 35.0 tps7a0525pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tps7a0525pdqnt x2son dqn 4 250 184.0 184.0 19.0 tps7a05285pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tps7a05285pdbvt sot-23 dbv 5 250 210.0 185.0 35.0 tps7a05285pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tps7a05285pdqnt x2son dqn 4 250 184.0 184.0 19.0 tps7a0528pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tps7a0528pdqnt x2son dqn 4 250 184.0 184.0 19.0 tps7a0530pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tps7a0530pdqnt x2son dqn 4 250 184.0 184.0 19.0 tps7a0531pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tps7a0531pdbvt sot-23 dbv 5 250 210.0 185.0 35.0 tps7a0533pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tps7a0533pdbvt sot-23 dbv 5 250 210.0 185.0 35.0 tps7a0533pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tps7a0533pdqnt x2son dqn 4 250 184.0 184.0 19.0 package materials information www.ti.com 2-aug-2018 pack materials-page 4 www.ti.com package outline c 0.4 max 0.18 0.13 0.35 typ 4x 0.25 0.15 0.35 typ b e a d 4221909/b 08/2018 dsbga - 0.4 mm max height yka0004 die size ball grid array notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. ball a1 corner seating plane ball typ 0.05 c 1 2 0.015 c a b symm symm b a scale 14.000 www.ti.com example board layout 4x ( 0.2) (0.35) typ (0.35) typ ( 0.2) metal 0.0325 max ( 0.2) solder mask opening 0.0325 min 4221909/b 08/2018 dsbga - 0.4 mm max height yka0004 die size ball grid array notes: (continued) 3. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number snva009 (www.ti.com/lit/snva009). symm symm land pattern example exposed metal shown scale:60x 1 2 a b non-solder mask defined solder mask details not to scale solder mask opening exposed metal solder mask defined (preferred) metal under solder mask exposed metal www.ti.com example stencil design (0.35) typ (0.35) typ 4x ( 0.21) (r0.05) typ metal typ 4221909/b 08/2018 dsbga - 0.4 mm max height yka0004 die size ball grid array notes: (continued) 4. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. symm symm solder paste example based on 0.075 mm - 0.1 mm thick stencil scale:60x 1 2 a b www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000 www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2 www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000 www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2 package outline dqn0004a x2son - 0.4 mm max height plastic small outline - no lead 4215302/e 12/2016 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. 4. features may not exist. recommend use of pin 1 marking on top of package for orientation purposes. 5. shape of exposed side leads may differ. 6. number and location of exposed tie bars may vary. www.ti.com b a seating plane c 0.08 pin 1 index area 0.1 c a b 0.05 c pin 1 id (optional) note 4 exposed thermal pad 1 2 3 4 1 1.05 0.95 1.05 0.95 0.4 max 2x 0.65 0.48 +0.12 -0.1 3x 0.30 0.15 0.3 0.2 4x 0.28 0.15 0.05 0.00 (0.11) note 5 note 6 note 6 5 (0.07) typ (0.05) typ example board layout dqn0004a x2son - 0.4 mm max height plastic small outline - no lead 4215302/e 12/2016 notes: (continued) 7. this package is designed to be soldered to a thermal pad on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271) . 8. if any vias are implemented, it is recommended that vias under paste be filled, plugged or tented. www.ti.com solder mask defined solder mask detail 0.05 min all around solder mask opening metal under solder mask land pattern example scale: 40x symm symm 1 2 3 4 4x (0.21) 4x (0.36) (0.65) (0.86) ( 0.48) see detail 4x (0.18) (0.22) typ exposed metal clearance 4x (0.03) exposed metal 5 example stencil design dqn0004a x2son - 0.4 mm max height plastic small outline - no lead 4215302/e 12/2016 notes: (continued) 9. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. www.ti.com solder paste example based on 0.075 - 0.1mm thick stencil exposed pad 88% printed solder coverage by area scale: 60x symm symm 1 2 3 4 solder mask edge 4x (0.21) 4x (0.4) (0.65) (0.9) ( 0.45) 4x (0.03) 4x (0.235) 4x (0.22) 5 important notice texas instruments incorporated (ti) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. ti ? s published terms of sale for semiconductor products ( http://www.ti.com/sc/docs/stdterms.htm ) apply to the sale of packaged integrated circuit products that ti has qualified and released to market. additional terms may apply to the use or sale of other types of ti products and services. reproduction of significant portions of ti information in ti data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such reproduced documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyers and others who are developing systems that incorporate ti products (collectively, ? designers ? ) understand and agree that designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that designers have full and exclusive responsibility to assure the safety of designers ' applications and compliance of their applications (and of all ti products used in or for designers ? applications) with all applicable regulations, laws and other applicable requirements. designer represents that, with respect to their applications, designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. designer agrees that prior to using or distributing any applications that include ti products, designer will thoroughly test such applications and the functionality of such ti products as used in such applications. ti ? s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, ? ti resources ? ) are intended to assist designers who are developing applications that incorporate ti products; by downloading, accessing or using ti resources in any way, designer (individually or, if designer is acting on behalf of a company, designer ? s company) agrees to use any particular ti resource solely for this purpose and subject to the terms of this notice. ti ? s provision of ti resources does not expand or otherwise alter ti ? s applicable published warranties or warranty disclaimers for ti products, and no additional obligations or liabilities arise from ti providing such ti resources. ti reserves the right to make corrections, enhancements, improvements and other changes to its ti resources. ti has not conducted any testing other than that specifically described in the published documentation for a particular ti resource. designer is authorized to use, copy and modify any individual ti resource only in connection with the development of applications that include the ti product(s) identified in such ti resource. no other license, express or implied, by estoppel or otherwise to any other ti intellectual property right, and no license to any technology or intellectual property right of ti or any third party is granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti products or services are used. information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. use of ti resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. ti resources are provided ? as is ? and with all faults. ti disclaims all other warranties or representations, express or implied, regarding resources or use thereof, including but not limited to accuracy or completeness, title, any epidemic failure warranty and any implied warranties of merchantability, fitness for a particular purpose, and non-infringement of any third party intellectual property rights. ti shall not be liable for and shall not defend or indemnify designer against any claim, including but not limited to any infringement claim that relates to or is based on any combination of products even if described in ti resources or otherwise. in no event shall ti be liable for any actual, direct, special, collateral, indirect, punitive, incidental, consequential or exemplary damages in connection with or arising out of ti resources or use thereof, and regardless of whether ti has been advised of the possibility of such damages. unless ti has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., iso/ts 16949 and iso 26262), ti is not responsible for any failure to meet such industry standard requirements. where ti specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. using products in an application does not by itself establish any safety features in the application. designers must ensure compliance with safety-related requirements and standards applicable to their applications. designer may not use any ti products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). such equipment includes, without limitation, all medical devices identified by the u.s. food and drug administration as class iii devices and equivalent classifications outside the u.s. ti may expressly designate certain products as completing a particular qualification (e.g., q100, military grade, or enhanced product). designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at designers ? own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated |
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